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Four-phase logic is a type of, and design methodology for, dynamic logic. It enabled non-specialist engineers to design quite complex ICs, using either PMOS or NMOS processes. It uses a kind of 4-phase clock signal. ==History== R. K. "Bob" Booher, an engineer at Autonetics, invented four-phase logic, and communicated the idea to Frank Wanlass at Fairchild Semiconductor; Wanlass promoted this logic form at General Instrument Microelectronics Division.〔 〕 Booher made the first working four-phase chip, the Autonetics DDA integrator, during February 1966; he later designed several chips for and built the Autonetics D200 airborne computer using this technique.〔 R. K. Booher, "(MOS GP Computer )," afips, pp.877, 1968 Proceedings of the Fall Joint Computer Conference, 1968 〕 In April 1967, Joel Karp and Elizabeth de Atley published an article "Use four-phase MOS IC logic" in ''Electronic Design'' magazine.〔 〕 In the same year, Cohen, Rubenstein, and Wanlass published "MTOS four phase clock systems."〔 〕 Wanlass had been director of research and engineering at General Instrument Microelectronics Division in New York since leaving Fairchild Semiconductor in 1964. Lee Boysel, a disciple of Wanlass〔 〕 and a designer at Fairchild Semiconductor, and later founder of Four-Phase Systems, gave a "late news" talk on a four-phase 8-bit adder device in October 1967 at the International Electron Devices meeting.〔 〕 J. L. Seely, manager of MOS Operations at General Instrument Microelectronics Division, also wrote about four-phase logic in late 1967.〔 〕 In 1968 Boysel published an article "Adder On a Chip: LSI Helps Reduce Cost of Small Machine" in ''Electronics'' magazine;〔 〕 Four-phase papers from Y. T. Yen also appear that year.〔 Y. T. Yen (1968) "A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation" ''IEEE Transactions on Computers'': C-17 Sept. 1968 〕〔 Y. T. Yen (1968) "Intermittent Failure Problems of Four-Phase MOS Circuits" ''IEEE Journal of Solid-State Circuits'': SC-4 No. 3 June. 1969 〕 Other papers followed shortly.〔 Hatt R. J., Jackets A. E. & Jarvis D. B. of Associated Semiconductor Manufacturers "Four-phase Logic Circuits using Integrated m-o-s Transistors" ''Mullard Technical Communication'': No 99 May 1969 〕 Boysel recalls that four-phase dynamic logic allowed him to achieve 10X the packing density, 10X the speed, and 1/10 the power, compared to other MOS techniques being used at the time (metal-gate saturated-load PMOS logic), using the first-generation MOS process at Fairchild. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Four-phase logic」の詳細全文を読む スポンサード リンク
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